MOS transistors with hybrid operation are known, which are of interest notably for electrostatic discharge (ESD) protection applications. A person skilled in the art will for example be able to refer to U.S. Pat. No. 9,019,666 (incorporated by reference) which describes this type of transistor.
These transistors are produced on bulk substrates. Now, electrical simulations have shown (see, for example, Galy, et al., “BIMOS transistor in thin silicon film and new solutions for ESD protection in FDSOI UTBB CMOS technology”, EUROSOI-ULIS 2015, 26-28 Jan. 2015, Bologna, Italy (incorporated by reference)), that there would be advantages from an electrical point of view in producing these transistors with hybrid operation on a substrate of FDSOI type for an ESD protection application.
However, the very small thickness of the semiconductive film (typically of the order of 7 nm) does not make it possible to directly produce a contact on an FDSOI substrate for this type of transistor.
U.S. application patent Ser. No. 15/041,593 filed Feb. 11, 2016 (corresponding to French Application for Patent No. 1556515), incorporated by reference, describes means that make it possible to produce a substrate contact by the use of additional junction-free transistor(s) as connection element(s). Although satisfactory, this solution can however, in some cases, generate spurious effects and offers an integration density which can prove limited in certain applications.